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Product Details

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Product Details

*The following are the basic parameters of the product, involving the characteristics of the product and its category

TYPEDESCRIPTION
Part StatusActive
RoHS StatusROHS3 Compliant
MountSurface Mount
ECCN CodeEAR99
Boundary ScanYES
Time@Peak Reflow Temperature-Max (s)NOT SPECIFIED
Peak Reflow Temperature (Cel)NOT SPECIFIED
PackagingTray
Factory Lead Time10 Weeks
Qualification StatusNot Qualified
TechnologyCMOS
Moisture Sensitivity Level (MSL)3 (168 Hours)
Published2010
Height Seated (Max)1.6mm
HTS Code8542.39.00.01
Terminal PositionBOTTOM
Terminal Pitch0.8mm
Terminal FormBALL
Supply Voltage1V
JESD-609 Codee1
Terminal FinishTin/Silver/Copper (Sn/Ag/Cu)
Contact PlatingCopper, Silver, Tin
Data Bus Width32b
Core ArchitectureARM
Length19mm
Number of I/O130
RAM Size256kB
Supply Voltage-Min (Vsup)0.95V
UV ErasableN
ArchitectureMCU, FPGA
Supply Voltage-Max (Vsup)1.05V
uPs/uCs/Peripheral ICs TypeMICROPROCESSOR CIRCUIT
Operating Temperature0°C~100°C TJ
Core ProcessorDual ARM? Cortex?-A9 MPCore? with CoreSight?
SubcategoryOther Microprocessor ICs
ConnectivityCANbus, EBI/EMI, Ethernet, I2C, MMC/SD/SDIO, SPI, UART/USART, USB OTG
Power Supplies11.8V
PeripheralsDMA
SeriesZynq?-7000
InterfaceCAN, EBI/EMI, Ethernet, I2C, MMC, SD, SDIO, SPI, UART, USART, USB
RAM (words)256000
Bus CompatibilityCAN; ETHERNET; I2C; SPI; UART; USB
Number of Terminations485
Number of Pins485
Additional FeaturePL BLOCK OPERATES IN 0.97V TO 1.03V SUPPLY
Frequency766MHz
Package / Case484-LFBGA, CSPBGA
Primary AttributesArtix?-7 FPGA, 74K Logic Cells

Manufacturer introduction

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