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*The following are the basic parameters of the product, involving the characteristics of the product and its category
| TYPE | DESCRIPTION |
|---|---|
| Part Status | Active |
| RoHS Status | RoHS Compliant |
| Surface Mount | YES |
| JESD-609 Code | e3 |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Packaging | Tray |
| Factory Lead Time | 10 Weeks |
| Qualification Status | Not Qualified |
| Technology | CMOS |
| Published | 2015 |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Terminal Pitch | 0.5mm |
| HTS Code | 8542.39.00.01 |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Terminal Finish | MATTE TIN |
| Supply Voltage | 1.2V |
| Power Supplies | 1.2V |
| Number of I/O | 200 |
| Number of Outputs | 200 |
| Number of Inputs | 200 |
| Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY |
| Length | 11mm |
| Width | 11mm |
| Subcategory | Field Programmable Gate Arrays |
| Speed | 166MHz |
| RAM Size | 64kB |
| Lifecycle Status | IN PRODUCTION (Last Updated: 2 weeks ago) |
| Architecture | MCU, FPGA |
| Supply Voltage-Min (Vsup) | 1.14V |
| Supply Voltage-Max (Vsup) | 1.26V |
| Flash Size | 256KB |
| Connectivity | CANbus, Ethernet, I2C, SPI, UART/USART, USB |
| Peripherals | DDR, PCIe, SERDES |
| Number of Terminations | 325 |
| Height Seated (Max) | 1.01mm |
| Number of Logic Cells | 56340 |
| Primary Attributes | FPGA – 50K Logic Modules |
| Package / Case | 325-TFBGA, CSPBGA |
| Additional Feature | LG-MIN, WD-MIN |
| JESD-30 Code | S-PBGA-B325 |
| Operating Temperature | 0?°C~85?°C TJ |
| Core Processor | ARM?? Cortex??-M3 |
| Series | SmartFusion??2 |
*The following components have specifications similar
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