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TYPE | DESCRIPTION |
---|---|
RoHS Status | Non-RoHS Compliant |
Surface Mount | YES |
Part Status | Obsolete |
Factory Lead Time | 12 Weeks |
Packaging | Tray |
Published | 2013 |
Qualification Status | Not Qualified |
JESD-609 Code | e0 |
Terminal Form | GULL WING |
Technology | CMOS |
Time@Peak Reflow Temperature-Max (s) | 20 |
Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
Number of Logic Blocks (LABs) | 24 |
Terminal Finish | Tin/Lead (Sn/Pb) |
Terminal Pitch | 0.5mm |
Terminal Position | QUAD |
HTS Code | 8542.39.00.01 |
Supply Voltage | 1.5V |
Number of Outputs | 66 |
Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY |
Subcategory | Field Programmable Gate Arrays |
Peak Reflow Temperature (Cel) | 225 |
Frequency | 80MHz |
Length | 28mm |
Width | 28mm |
Core Architecture | ARM |
Operating Temperature | -40°C~100°C TJ |
Number of Terminations | 208 |
Number of Pins | 208 |
RAM Size | 64kB |
Core Processor | ARM? Cortex?-M3 |
Height Seated (Max) | 4.1mm |
Architecture | MCU, FPGA |
Peripherals | DMA, POR, WDT |
Supply Voltage-Max (Vsup) | 1.575V |
Package / Case | 208-BFQFP |
Supply Voltage-Min (Vsup) | 1.425V |
Flash Size | 512KB |
Number of Equivalent Gates | 500000 |
Series | SmartFusion? |
Primary Attributes | ProASIC?3 FPGA, 500K Gates, 11520 D-Flip-Flops |
Connectivity | Ethernet, I2C, SPI, UART/USART |
Base Part Number | A2F500M3G |
Number of I/O | MCU – 22, FPGA – 66 |
Power Supplies | 1.51.82.53.3V |
Interface | Ethernet, I2C, SPI, UART, USART |
Organization | 11520 CLBS, 500000 GATES |
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