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*The following are the basic parameters of the product, involving the characteristics of the product and its category
TYPE | DESCRIPTION |
---|---|
Part Status | Active |
RoHS Status | RoHS Compliant |
Surface Mount | YES |
Packaging | Tray |
Published | 2013 |
Factory Lead Time | 10 Weeks |
Qualification Status | Not Qualified |
Technology | CMOS |
Peak Reflow Temperature (Cel) | 260 |
Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
Time@Peak Reflow Temperature-Max (s) | 30 |
Terminal Pitch | 0.5mm |
HTS Code | 8542.39.00.01 |
Terminal Position | BOTTOM |
Frequency | 100MHz |
Terminal Form | BALL |
JESD-609 Code | e1 |
Terminal Finish | Tin/Silver/Copper (Sn/Ag/Cu) |
Supply Voltage | 1.5V |
Operating Supply Voltage | 1.5V |
Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY |
Length | 11mm |
Width | 11mm |
Subcategory | Field Programmable Gate Arrays |
Number of Outputs | 78 |
Number of Inputs | 78 |
Core Architecture | ARM |
Operating Temperature | -40°C~100°C TJ |
RAM Size | 64kB |
Core Processor | ARM? Cortex?-M3 |
Height Seated (Max) | 1.05mm |
Architecture | MCU, FPGA |
Peripherals | DMA, POR, WDT |
Max Supply Voltage | 1.575V |
Number of Terminations | 288 |
Min Supply Voltage | 1.425V |
Flash Size | 512KB |
Number of Equivalent Gates | 500000 |
Series | SmartFusion? |
Connectivity | EBI/EMI, Ethernet, I2C, SPI, UART/USART |
Primary Attributes | ProASIC?3 FPGA, 500K Gates, 11520 D-Flip-Flops |
Interface | EBI/EMI, Ethernet, I2C, SPI, UART, USART |
Base Part Number | A2F500M3G |
Package / Case | 288-TFBGA, CSPBGA |
Number of I/O | MCU – 31, FPGA – 78 |
JESD-30 Code | S-PBGA-B288 |
Power Supplies | 1.51.82.53.3V |
Organization | 11520 CLBS, 500000 GATES |
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