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*The following are the basic parameters of the product, involving the characteristics of the product and its category
| TYPE | DESCRIPTION |
|---|---|
| Part Status | Active |
| RoHS Status | RoHS Compliant |
| Surface Mount | YES |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Factory Lead Time | 8 Weeks |
| Packaging | Tray |
| Qualification Status | Not Qualified |
| Technology | CMOS |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| HTS Code | 8542.39.00.01 |
| Terminal Position | BOTTOM |
| Terminal Pitch | 0.8mm |
| Terminal Form | BALL |
| JESD-609 Code | e1 |
| Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY |
| Subcategory | Field Programmable Gate Arrays |
| Supply Voltage | 1.1V |
| Length | 23mm |
| Width | 23mm |
| Operating Temperature | 0°C~85°C TJ |
| Published | 2018 |
| RAM Size | 64kB |
| Terminal Finish | TIN SILVER COPPER |
| Number of Terminations | 672 |
| Architecture | MCU, FPGA |
| Speed | 600MHz |
| Peripherals | DMA, POR, WDT |
| Height Seated (Max) | 1.85mm |
| Power Supplies | 1.11.2/3.32.5V |
| Number of Outputs | 145 |
| Number of Inputs | 145 |
| Supply Voltage-Max (Vsup) | 1.13V |
| Core Processor | Dual ARM? Cortex?-A9 MPCore? with CoreSight? |
| JESD-30 Code | S-PBGA-B672 |
| Supply Voltage-Min (Vsup) | 1.07V |
| Connectivity | CANbus, EBI/EMI, Ethernet, I2C, MMC/SD/SDIO, SPI, UART/USART, USB OTG |
| Number of Logic Cells | 85000 |
| Series | Cyclone? V SE |
| Package / Case | 672-FBGA |
| Number of I/O | MCU – 181, FPGA – 145 |
| Primary Attributes | FPGA – 85K Logic Elements |
| Base Part Number | 5CSEBA5 |
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